Algorithms, Big Data, and Computing are the ABCs of the AI Era. Technology scaling and architectural innovations are the key drivers for the performance improvement of AI chips. In this talk, the speaker will discuss the challenges of the computing needs in the AI era, and present a series of his work in technology-driven architecture innovations, including novel architectures with die-stacking 3D ICs, near-data computing, and in-memory computing, as well as industrial tech transfer of the research outcomes in these directions.

Yuan Xie is the Fang Professor of Engineering and Chair Professor of ECE department at HKUST. He received BS degree in Electronic Engineering from Tsinghua University and Ph.D. degree in Computer Engineering from Princeton University. Before joining HKUST, he was a Professor at the University of California, Santa Barbara (UCSB), a Professor at the Pennsylvania State University. He also has rich industry experience with AMD, IBM Microelectronics, and Alibaba Group. Yuan Xie is a Fellow of IEEE, ACM, and AAAS, and a recipient of many awards, including NSF CAREER Award (2006), IEEE Computer Society Edward J. McCluskey Technical Achievement Award (2021), and IEEE CAS Society Industrial Pioneer Award (2023)

Dynamic voltage scaling (DVS) is a technique that varies the system's operating voltage and hence clock frequency based on the computation demand in order to achieve power and energy efficiency. It has been adopted by today's computing and communication devices, from smartphones and mobile sensors to data centers and cloud servers. In this talk, I will share our research experiences and results on DVS in the past 25+ years. I will start with a description of the essence of DVS in trading execution speed (or complete time) for power and energy saving. Then I will present the theoretical framework and practical solutions for DVS-enabled systems. In the second half, we will switch to the security aspect, where I will discuss the security vulnerabilities associated with DVS, highlighting our VoltJockey attacks that have successfully broken the trusted execution environment provided by ARM TrustZone, Intel SGX, and Nvidia GPU Cloud. I will also report our recent works on leveraging DVS to enhance the security of devices and machine learning models. The talk concludes with a short summary on the lessons we have learned in the development and implementation of DVS.

Gang Qu is currently a professor in the Department of Electrical and Computer Engineering and the Institute of System Research at the University of Maryland, College Park. He leads the Maryland Embedded Systems and Hardware Security Lab (MeshSec) and the Wireless Sensor Laboratory. His recent research activities are on hardware security and trust, artificial intelligence, security in vehicular systems, and the Internet of Things. He is also known for his work on wireless sensor networks, low power and energy efficient embedded system design.
Dr. Qu has served as the general chair or program chair for 18 conferences/symposiums/workshops. He serves as an associate editor for IEEE TCAD, IEEE TCAS II, IEEE TETC, ACM TODAES, Integration the VLSI Journal, and JCST. Dr. Qu is an enthusiastic teacher and has taught many security courses, including a popular MOOC on Hardware Security through Coursera. Dr. Qu is a co-founder of IEEE Hardware Security and Trust Technical Committee and a fellow of IEEE.

Coarse-Grained Reconfigurable Arrays (CGRA) are programmable, domain-agnostic accelerators that can be morphed and instantiated into specialized accelerators on-the-fly via software. They offer ASIC-like efficiency while promising high adaptability through compile-time reconfiguration. The central challenge is the efficient spatio-temporal mapping of applications expressed in high-level programming languages to the accelerator. Unfortunately, unlike FPGA, the CGRA design tools are in their infancy. In this talk, I will present Morpher, an open-source end-to-end compilation, simulation, and validation framework crafted to assist design space exploration and application-level development of CGRA-based systems. At the heart of Morpher is an innovative portable and scalable compiler. This compiler can synthesize complex application kernels onto any user-specified CGRA architecture through a Graph-Neural Network (GNN) based approach coupled with hierarchical mapping abstractions. Thus it can produce superior quality mapping in just a fraction of the compilation time compared to state-of-the-art techniques. We believe Morpher will act as a catalyst, pushing forward the boundaries of CGRA innovations.

Tulika Mitra is the Vice-Provost (Academic Affairs) and Provost's Chair Professor of Computer Science at the National University of Singapore (NUS). She received her PhD from Stony Brook University in 2001. Her research focuses on the design automation of smart, energy-efficient, safety-critical embedded computing systems. Her work is characterized by a systems-centric approach spanning hardware and software that has notably advanced accelerator design, power/thermal management in heterogeneous computing systems, and WCET analysis of real-time systems. Her service contributions include Editor-in-Chief of ACM Transactions on Embedded Computing Systems, General/Program Chair of ICCAD, General Chair of ESWEEK among others. Tulika has been recognized with the Embedded Systems Week (ESWEEK) Test-of-Time Award, Indian Institute of Science S. K. Chatterjee Award for Outstanding Woman Researcher, IEEE Computer Society Distinguished Contributor, several best paper awards or candidates in top conferences, IEEE CEDA Outstanding Service, and ACM SIGDA Distinguished Service Award.

TODO

Takashi Sato received B. E. and M. E. degrees from Waseda University, Tokyo, Japan, and a Ph. D. degree from Kyoto University, Kyoto, Japan. He was with Hitachi, Ltd., Tokyo, Japan, from 1991 to 2003, with Renesas Technology Corp., Tokyo, Japan, from 2003 to 2006, and with the Tokyo Institute of Technology, Yokohama, Japan. In 2009, he joined the Graduate School of Informatics, Kyoto University, Kyoto, Japan, where he is currently a professor. He was a visiting industrial fellow at the University of California, Berkeley, from 1998 to 1999. His research interests include CAD for nanometer-scale LSI design, fabrication-aware design methodology, and performance optimization for variation tolerance. Dr. Sato is a senior member of the IEEE, the member of the ACM, and the Institute of Electronics, Information and Communication Engineers (IEICE). He received the Beatrice Winner Award at ISSCC 2000 and the Best Paper Award at ISQED 2003.

After decades of advancements, artificial intelligence algorithms have become increasingly sophisticated, with sparse computing playing a pivotal role in their evolution. This talk will first review and summarize the characteristics of sparsity in AI 1.0 & 2.0. Subsequently, three representative AI algorithms - Convolutional Neural Network, Graph Neural Network, and Large Language Model, along with their sparse computing optimizations, will be discussed. By analyzing the similarities and differences of these AI algorithms, we will propose the development trend of sparse computing. Finally, this talk will envision a future, where a coordinated dataflow, instruction-set-architecture, and hardware co-design approach would provide a great opportunity for efficient and general processing of various sparsity and sparse AI algorithms.

Yu Wang, professor, IEEE fellow, chair of the Department of Electronic Engineering of Tsinghua University, dean of Institute for Electronics and Information Technology in Tianjin, and vice dean of School of information science and technology of Tsinghua University. His research interests include the application specific heterogeneous computing, processing-in-memory, intelligent multi-agent system, and power/reliability aware system design methodology. Yu Wang has published more than 80 journals (60 IEEE/ACM journals) and 200 conference papers in the areas of EDA, FPGA, VLSI Design, and Embedded Systems, with the Google citation more than 17,000. He has received four best paper awards and 12 best paper nominations. Yu Wang has been an active volunteer in the design automation, VLSI, and FPGA conferences. He will serve as TPC chair for ASP-DAC 2025. He serves as the editor of important journals in the field such as ACM TODAES and IEEE TCAD and program committee member for leading conferences in the top EDA and FPGA conferences.

This talk aims at introducing the multi-grained re-configurable computing platforms which are elastic in both of space and time domains. It is expected to explore the disruptive computer architectures for ultra-high speed, low cost, and flexible tensor computations without any benefitting of Moore's Law. For this purpose, (1) the multi-grained re-configurable architecture is developed on the basis of our novel neural network topology seen as "DiaNet" (addressing space-elastic); (2) an innovative mechanism for data processing is explored by the snapshot (or accumulative, optionally) observation of spiking (addressing time-elastic). By merging (1) and (2), arbitrary complex AI tasks can be migrated onto our platforms with any specific speed-quality constraints, which can even be within one clock cycle (seen as "flash computing"). For powering ubiquitous computations, the conventional trade-off among the performance, speed, cost is expected to be broken through.

Renyuan Zhang (Senior Member, IEEE) received the B.E degree from Tongji University in 2007; the M.E. degree from Waseda University in 2010 and the Ph.D. degree from the University of Tokyo in 2013. He was an assistant professor with Japan Advanced Institute of Science and Technology from 2013 to 2017. He has been an assistant professor with Nara Institute of Science and Technology (NAIST) and the PRESTO researcher with Japan Science and Technology Agency since 2017 and 2018, respectively. From 2021, he serves NAIST (Japan) as an associate professor. His research interests include analog-digital-mixed circuits, approximate computing, high performance computing architectures, and hardware implementation of AI.